In semiconductor processing, through-silicon vias (TSV) are often used to provide electrical connection between adjacent semiconductor dies. Fabrication of TSVs involves etching a deep hole into a semiconductor wafer or substrate and filling the resulting hole with a conductive fill such as copper. The wafer is then thinned from its back side until the conductive fill is exposed, and back side bond pads are then formed over the exposed TSV for electrical contact. Typically, the wafer is thinned using a chemical mechanical planarization (CMP) process.
One challenge of using back side CMP processes to expose TSVs is that they often fail to achieve the requisite planarity. For example, CMP processes may underpolish areas where TSVs are located, but overpolish other areas. In either case, this can introduce undesired topography, and can deleteriously affect performance of the TSVs. For example, underpolishing may leave residual material that interferes with the electrical contact of the TSVs. Further, varying topography of the back side of a wafer can lead to further problems for inspection and metrology. Accordingly, there remains a need to develop practical methods to improve back side exposure of TSVs.